This application claims the priority benefit of Taiwan application serial no. 89119795, filed Sep. 26, 2000.
1. Field of Invention
The present invention relates to a method of manufacturing semiconductor devices. More particularly, the present invention relates to a method of forming the gate of a stacked-gate non-volatile memory device such that effective area of the inter-gate dielectric layer (the dielectric layer between the control gate and the floating gate) inside the gate is increased.
2. Description of Related Art
All stacked-gate non-volatile memory such as erasable programmable read-only-memory (EPROM), electrically erasable programmable read-only-memory (EEPROM) and flash memory can hold data without the application of a voltage. Hence, stacked-gate non-volatile memory is ideal for storing frequently used and relatively permanent programs.
In general, the current-voltage characteristic of a stacked-gate non-volatile memory device can be inferred from the current-voltage characteristic and the capacitive coupling effects of a conventional metal-oxide-semiconductor device. Typically, the larger the capacitive coupling ratio of the non-volatile memory device, the lower will be the operating voltage required.
FIG. 1A is a diagram showing the layout of a conventional stacked-gate non-volatile flash memory device after the floating gate is patterned. FIG. 1B is a diagram showing the gate layout of the device shown in FIG. 1A. FIG. 2 is a cross-sectional diagram along line II-IIxe2x80x2 of FIG. 1B. As shown in FIGS. 1A and 1B, the layout includes a gate region 58 and a non-gate region 60. FIG. 2 is in fact a cross-sectional diagram showing details of the gate region 58 and neighboring region according to FIG. 1. As shown in FIG. 2, a gate structure is formed above a substrate. The substrate has a device structure therein. The device structure includes a semiconductor substrate 20, a source terminal 22 and a drain terminal 23. The gate structure includes a gate dielectric layer 24, a conductive layer 26, a conductive layer 50, a dielectric layer 52 and a conductive layer 54. The conductive layer 54 at least includes one layer. The gate dielectric layer 24 is a dielectric layer between the gate conductive layer 26 and the substrate 20. The conductive layer 26 and the conductive layer 50 together constitute a floating gate. The dielectric layer 52 is an inter-gate dielectric layer. The conductive layer 54 is a control gate.
A conventional stacked-gate type non-volatile flash memory device has altogether four contact capacitors. They are the contact capacitor CFG between the floating gate (the conductive layer 26 and the conductive layer 50) and the control gate (the conductive layer 54), the contact capacitor CB between the floating gate (the conductive layer 26 and the conductive layer 50) and the substrate (the semiconductor substrate 20), the contact capacitor CS between the floating gate (the conductive layer 26 and the conductive layer 50) and the source terminal 22 and the contact capacitor CD between the floating gate and the drain terminal 23.
The capacitive coupling ratio can be represented by the following formula:       Capacitive    ⁢          xe2x80x83        ⁢    coupling    ⁢          xe2x80x83        ⁢    ratio    =            C      FG                      C        FG            +              C        B            +              C        S            +              C        D            
According to the above formula, when the capacitance of the contact capacitor CFG between the floating gate (the conductive layer 26 and the conductive layer 50) and the control gate (the conductive layer 54) increases, the capacitive coupling ratio also increases.
In general, the capacitive coupling ratio can be increased by increasing the effective area of the inter-gate dielectric layer, lowering the thickness of the inter-gate dielectric layer and increasing the dielectric constant k of the inter-gate dielectric layer.
However, the inter-gate dielectric layer must have sufficient thickness to prevent electrons trapped inside the floating gate (the conductive layer 26 and the conductive layer 50) from entering into the control gate (the conductive layer 54) and resulting in device failure. On the other hand, increasing the dielectric constant of the inter-gate dielectric layer involves the use of new material and equipment for processing the material. Hence, the process cannot be easily implemented. Ultimately, the only option for increasing the capacitive coupling ratio falls back to increasing the effective surface area of the inter-gate dielectric layer so that the capacitance of the contact capacitance CFG between the floating gate (the conductive layer 26 and the conductive layer 50) and the control gate (the conductive layer 54) is increased.
However, as shown in FIG. 1A, 1B and 2, the conductive layer 50 is of the stacked-type. Hence, the increase in effective surface area is quite limited. Furthermore, when the dielectric layer 52 and the conductive layer 54 are patterned, the conductive layer 54 in the non-gate region 60, the dielectric layer 52, the conductive layer 50 and the conductive layer 26 must be removed simultaneously. Since the conductive layer 50 has a definite thickness, much thicker layer of the dielectric layer 52 needs to be removed by etching in the vertical direction than in the horizontal direction. Hence, some residues from the dielectric layer 52 are likely to remain.
In addition, signal storage in a dynamic random access memory is achieved through selectively charging and discharging of the capacitors on the surface of a semiconductor substrate. The execution of read/write operation is effected by moving electric charges into or away from a capacitor via a transfer field effect transistor connected to a bit line.
Capacitor is one of the principle components in a dynamic random access memory. Any reduction in capacitance accompanied by a reduction in memory cell area is likely to limit memory density. A reduction in memory cell capacitance will increase read-out difficulties and soft errors. Moreover, the use of low operating voltage may lead to large power consumption. An effective means of increasing capacitance is to increase the effective surface area of the dielectric layer between the upper and the lower electrode of a capacitor.
FIG. 3 is a cross-sectional view showing a conventional stack capacitor. As shown in FIG. 3, the stack capacitor includes a semiconductor substrate 80 having a device structure 82 therein. A dielectric layer 84 is above the semiconductor substrate 80 and the dielectric layer has a via opening 86 that exposes a portion of the device structure 82. The stack capacitor also includes the lower electrode 88 of a conventional stack transistor. The lower electrode 88 fills the via opening 86 and covers a portion of the dielectric layer 84 around the via opening 86. The lower electrode 88 has a stacked-type profile. Due to shape limitation, such a lower electrode 88 only has moderate surface area.
A cylindrical capacitor has a greater surface area but processing demands more masking operations, and hence increases production time and complexity.
Accordingly, one object of the present invention is to provide a transistor gate structure and a method of forming the transistor gate capable of increasing effective surface area of the inter-gate dielectric layer inside a transistor gate and reducing etching thickness of the inter-gate dielectric layer in the vertical direction.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a transistor gate. First, a gate dielectric layer is formed over a substrate. The lower section of a floating gate is formed over the gate dielectric layer. A source/drain region is formed in the substrate, one on each side of the lower section of the floating gate. A first dielectric layer is formed over the substrate. The first dielectric layer has a via opening that exposes the upper portion of the lower section of the floating gate. A conductive material layer is next formed over the first dielectric layer. The conductive material layer fills the via opening. The conductive material layer is patterned to expose the first dielectric layer outside the via opening, thereby forming a first conductive layer. The first conductive layer at least fills the via opening. The first conductive layer has a slant external sidewall. A mask material layer is formed covering the first conductive layer. A planarization is carried out to remove a portion of the mask material layer, thereby forming a first etching mask layer. The upper portion of the first conductive layer is also exposed after the planarization operation. Using the first etching mask layer as an etching mask, an anisotropic slant etching is carried out to etch the first conductive layer to a predefined depth so that the upper section of the floating gate is formed. The upper section of the floating gate has an upper section opening. The first etching mask layer is then removed.
In the aforementioned method, the first conductive layer has slant external sidewalls. The first etching mask layer covers the first dielectric layer not covered by the first conductive layer. Furthermore, the first etching mask layer completely covers the slant external sidewalls and the upper portion not covered by the first conductive layer. Hence, the first etching mask layer can serve as an etching mask in the anisotropic slant angle etching to form the upper section of the floating gate. Since there is no need to use a photomask to pattern the upper section of the floating gate, one photomask operation is saved.
In addition, since the upper section of the floating gate has an upper portion opening. The upper section of the floating gate has bigger area than a conventional stacked-type floating gate. Moreover, the upper section of the floating gate is formed by performing anisotropic slant angle etching of the first conductive layer having slant external sidewalls using the first etching mask layer as a mask. Ultimately, the upper section of the floating gate has slant external and internal sidewalls.
After the first etching mask layer is removed, a second dielectric layer conformal to the profile of the upper section of the floating gate is formed. At least a second conductive layer is formed over the second dielectric layer. A patterned second etching mask layer is formed over the second conductive layer. The pattern runs across a portion of the upper section of the floating gate. Using the second etching mask layer as a mask, an anisotropic etching is conducted sequentially etching the second conductive layer, the second dielectric layer, the upper section of the floating gate and the lower section of the floating gate. Hence, a portion of the first dielectric layer and the gate dielectric layer under the lower section of the floating gate is exposed. After the second dielectric layer is etched, an inter-gate dielectric layer is formed above the upper section of the floating gate. After the second conductive layer is etched, a control gate structure layer is formed above the inter-gate dielectric layer. Finally, the second etching mask layer is removed.
In the aforementioned method, the inter-gate dielectric layer and the upper section of the floating gate are conformal. Therefore, effective surface area of the inter-gate dielectric layer is increased leading to better gate performance such as increasing the capacitance between the floating gate and the control gate.
In addition, the gate-forming method includes an anisotropic etching step to etch the inter-layer dielectric layer. Because the inter-gate dielectric layer has slant sidewalls similar to the one on the upper section of the floating gate, etching thickness in the vertical direction is reduced. Consequently, the process of removing inter-gate dielectric layer in the non-gate region is easier.
The first conductive layer includes a polysilicon layer. The conductive layer has slant external sidewalls forming an angle of between 60xc2x0 to 90xc2x0 with the horizontal. The first conductive layer covers, for example, the first dielectric layer around the via opening. The mask layer can be, for example, a photoresist layer, a spin-on glass layer, an oxide layer, a silicon nitride layer, an ion-containing oxide layer, an ion-containing silicon nitride layer, a boron-silicate glass layer or a silicon-oxygen containing organic layer. The planarization step can be carried out by back etching or chemical-mechanical polishing. The etching angle in the anisotropic etching step is between 60xc2x0 to 90xc2x0 with respect to the horizontal. The predefined depth is at least 30% of the thickness of the conductive layer, for example.
This invention also provides a transistor gate structure on a substrate. The substrate includes a source/drain terminal. The gate structure includes a gate dielectric layer above a portion of the substrate. A lower section of a floating gate is above the gate dielectric layer. A dielectric layer having a via opening that exposes the upper portion of the lower section of the floating gate is above the substrate. An upper section of the floating gate fills the via opening. The upper section and the lower section of the floating gate are electrically connected. The upper section of the floating gate has slant external sidewalls. The upper section of the floating gate further has an opening above the via opening. The upper section opening has slant interior sidewalls. The upper section opening of the floating gate has a pre-defined depth. A conformal inter-gate dielectric layer is above the upper section of the floating gate. A control gate is above the inter-gate dielectric layer.
In the aforementioned gate structure, the upper section of the floating gate has slant external sidewalls and the upper section opening of the floating gate has slant interior sidewalls. Hence, effective surface area in the upper section of the floating gate is increased. In addition, since the inter-gate dielectric layer is conformal to the profile of the upper section of the floating gate, effective surface area of the inter-gate dielectric layer is also increased. Moreover, the slant sidewalls render the removal of inter-gate dielectric layer in the non-gate region much easier. In brief, performance such as the capacitance between the floating gate and the control gate is increased due to the increase in effective surface area of the inter-gate dielectric layer.
Similarly, the method and structure of this invention can be applied to increase the capacitance of capacitor in a dynamic random access memory. In a dynamic random access memory capacitor, the inter-gate dielectric layer can be regarded as a capacitor dielectric layer, the floating gate can be regarded as a lower electrode while the control gate can be regarded as an upper electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.